Field of the Invention
The invention relates to a method for producing a memory cell in an integrated circuit starting from a whole-area silicon layer on a dielectric.
Memory cells are EEPROMs and flash EEPROMs. The silicon layer may be monocrystalline, polycrystalline or amorphous silicon. The dielectric which is used is usually silicon dioxide, for example as a gate oxide, or silicon nitride.
In the production of memory cells of that type, a polysilicon layer for a following structuring on a dielectric is generally produced in the course of the first method steps. The desired structuring, in particular of transistor gates, is carried out through the use of photolithography. The etching processes which are used in that case make very high requirements of the photoresist. The wet-chemical etching processes, in particular, produce relatively large, greatly varying undercuts and lead, in principle, to concave polysilicon edges which can only be treated with difficulty from the standpoints of production engineering and planarization.
In polysilicon etching processes, there is the risk of the gate oxide situated under the polysilicon becoming damaged. Since, moreover, the selectivity between the polysilicon and the silicon oxide is insufficient during etching, in a manner dictated by the system, the gate oxide is thinned in an unreproducible manner outside the gate regions in the source/drain regions which are to be produced later, with the result that the gate oxide, for defined source/drain implantation, has to be completely removed and replaced by an oxide that is to be newly formed. That necessitates a further wet-chemical etching process.
The last-mentioned etching produces a hollow groove in the gate oxide under the polysilicon gate edge, which produces a nonhomogeneous, difficult-to-control transition from the gate to the source/drain region with corresponding yield and reliability risks for the transistor. With regard to cleaning and to the oxidation behavior, such a hollow groove can only be controlled with difficulty in terms of process engineering. In particular, the insulation strength of an insulation oxide, formed thereon, with respect to a second polysilicon layer, for example in an EEPROM process, is adversely influenced by this fact.
Furthermore, for the purpose of producing MOS transistors, German Published, Non-Prosecuted Patent Application 27 39 662 discloses covering the silicon layer with a layer which serves as an oxidation protection, structuring the oxidation protection layer through the use of photolithography in order to produce a mask through the use of etching the oxidation protection layer and uncovering the polysilicon in the unmasked regions, and converting the polysilicon in the uncovered regions into silicon dioxide through the use of local oxidation.
IEEE Transactions on Electron Devices, Vol. ED 28, No.1, January 1981, pages 77-82 and Vol. ED 31, No.10, October 1984, pages 1413 to 1419 describes the production of a MOS circuit and of an EPROM. Furthermore, Published Japanese Patent Application 57-42169 and Published European Patent Application 0 294 699 A2 describe methods for producing memory cells. However, a relatively large number of method steps are required for producing a dielectric.